Field of Disclosure
Disclosed aspects relate to forecasting behavior of caches using a hypothetical cache to emulate cache behavior. In exemplary aspects, real-time dynamic modifications of characteristics of a real cache may be based on the forecasted behavior of the real cache.
Background
Some processing systems include one or more multiprocessor integrated circuits (i.e., chips). The multiprocessor chips include multiple processor cores that are interconnected with each other. Each processor core is supported by one or more caches, which are small high speed memories, usually Static Random Access Memory (SRAM), that contain the most recently accessed data of main memory. Caches store data files, called cache lines or cache blocks.
When a requesting processor core needs access to a particular cache line the requesting processor core first looks in its own cache. If the requesting processor core finds the cache line in its own cache, a cache hit has occurred. However, if the requesting processor core does not find the cache line in its own cache, a cache miss has occurred. When a cache miss occurs caches associated with other processor cores are checked to determine whether any of the other caches have the requested cache line. If the requested cache line is located in another processor core's cache, the other processor core's cache can provide the cache line to the requesting processor core. If the other caches do not have the requested cache line, the requesting processor core has to access the requested data file from main memory.
Having to access data from main memory as a result of a cache miss can have a significant performance impact for the processing system.